Duty-Cycle Independent Half-Delay-Line All-Digital Delay Locked Loop
碩士 === 國立中正大學 === 電機工程所 === 96 === A half-delay-line fast skew-compensation circuit (HDSC) with duty cycle independent is presented. Due to the duty cycle of some Intellectual Property (IP) is not ideal 50% output. We utilize the scheme to make sure the data can be synchronous on the SoC. The struct...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45315601174337427651 |