A System Architecture Exploration on the Configurable HW/SW Co-design for H.264 and MPEG-2 Video Decoder

• Main Authors: Ting-Yu Huang, 黃鼎育
• Other Authors: Jiun-In Guo
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/92957450042914596200

碩士 === 國立中正大學 === 資訊工程所 === 96 === In this thesis we focus on the design methodology to propose a design which is more flexible than ASIC solution and more efficient than the processor-based solution. According to the user’s requirement, user can modify the system parameters to configure the tradeoff between performance and cost. In order to achieve the mentioned features, we propose some optimization method to improve H.264 decoder software performance and provide the hardware accelerators and various firmware libraries corresponding to them for users. Besides, we propose the DEM controller to integrate the reference software and the hardware accelerators, and use the common AMBA bus protocol to make it as the portable system. In addition, we do some explorations to analyze the tradeoff between performances and cost such as software and hardware partition exploration, memory access and bus bandwidth exploration According to the result of explorations, we propose some solutions for different resolution of video applications to fit the best tradeoff between performance and cost. Finally, we extend our software and hardware partition system to MPEG-2 to support TV broadcasting applications.