Improving Redundant Via Insertion Rate at Pins with Multilevel Router
碩士 === 元智大學 === 資訊工程學系 === 95 === Appling redundant via(RV) insertion to a design is the most effective way for improving the manufacturing yield and circuits operating reliability. Previous work has done great jobs that the insertion rate is wonderful enough except the lowest layer, via1. We figure...
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54358569118790271670 |
| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 95 === Appling redundant via(RV) insertion to a design is the most effective way for improving the manufacturing yield and circuits operating reliability.
Previous work has done great jobs that the insertion rate is wonderful enough except the lowest layer, via1. We figured out this problem that no one has ever mentioned before and developed a so called Double-Via(DV)-Driven standard cell library compatible with the commercial one(UMC018). Our intent to redesign a cell library is hoping that the insertion rate of on-pin-via1s can be increased by reserving the sufficient space for a redundant via insertion at all pins.
Because the commercial router can not understand our intention upon cell pins, we also implemented a so called DV-aware router embedded some awareness features dedicated for increasing insertion rate of via1 at pins.
Experimental results show that the DV-aware router importing our library can improve up to 32% via1 insertion rate in average against the commercial one. The average overall insertion rate also gains up to 9% improvement. Besides, there is no significant performance impact when vias are doubling.
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