| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 95 === Power dissipation has become an important issue in VLSI design and testing. Especially in Scan-based architectures are expensive in power consumption during scanning in test vectors to the circuit. In the scan based circuit, the spurious transitions will be produced by scan flip-flops during scan cycles. The spurious transition will dissipate more power and lead to yield loss or decrease the reliability of the circuit under test.
In the thesis, we propose a method to reduce the power dissipation during scan test by don’t care bits assignment. Approach based on induced activity function. The induced activity function is used to estimate the influence of each scan cell in a test pattern on the circuit. A scan cell with high influence will induce more transitions than those with low influence. Therefore, we will try to make more gates in the circuit stabilize and make the few spurious transitions during testing. By the algorithm, we estimate the influence of each scan cell and assign it’s value accordingly. By this way, we can decrease our power dissipation during testing. This method needs not any extra hardware supporting, therefore there are no area overhead and performance loss in the proposed approach.
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