H.264 Main Profile Encoding Implementation on Dual Core SoC

• Main Authors: Ming-Geng Shiau, 蕭明耕
• Other Authors: Ching-Lung Su
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/22939659117334565898

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 95 === In this thesis, we extended a high quality and low complexity integer motion estimation algorithm for Bi-directional multiple reference frames, and implemented this algorithm on scalable video coding (SVC). In the fractional motion estimation, we have proposed two algorithms--one is for DSP; the other is for the hardware. The optimization of JM source code and integration of all motion estimation algorithms improve efficiency on dual core SoC. Under the H.264 QCIF, CIF, and D1 form, compared with full search, Main Profile integer motion estimation algorithm reduce 0.06dB, 0.1dB, and 0.159dB quality, decrease 96.69%, 95.93%, and 96.69% computation complexity, fractional motion estimation algorithm reference single frame for DSP reduce 0.121dB, 0.113dB, and 0.011dB quality, decrease 53% computation complexity, fractional motion estimation algorithm reference multiple frames for DSP reduce 0.107dB, 0.114dB, and 0.044dB quality, decrease 53% computation complexity, Main Profile fractional motion estimation algorithm for DSP reduce 0.13dB, 0.108dB, and 0.083dB quality, decrease 53% computation complexity; H.264 Main Profile fractional motion estimation for hardware design reduce 0.036dB, 0.069dB, and -0.024dB quality, decrease 30.86%, 33.81%, and 31.95% computation complexity; Under the SVC QCIF, CIF, D1 form, compared with full search, integer motion estimation algorithm reduce 0.0032dB, 0.003dB, 0.0053dB quality, decrease 93.13%, 88.57%, and 93.13% computation complexity, fractional motion estimation algorithm for DSP reduce 0.0197dB, 0.0257dB, and 0.0336dB quality, decrease 53% computation complexity, fractional motion estimation algorithm for hardware design reduce 0.0046dB, 0.0028dB, and 0.0016dB quality, decrease 34.24%, 34.71%, and 32.3% computation complexity. When the optimization code and integration of all algorithms are carried out on dual SoC, the speed would be improved by 20 times.