| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 95 === The theorem of the Finite Field has already been generally applied to a lot of places at present. Major application is the error correcting code in the communication system, and the Reed-Solomon code is a quite important one among them. There are a lot of operation units in GF(2^m) in Reed-Solomon decoder. And the architectures will influence the circuit characteristic of the whole decoder deeply, so can make to adopt the proper architecture to improve efficiency of the decoder.
The division part has the highest complexity in Finite Field. For calculation inverses, we propose an algorithm of Adjoint Matrix that solves the linear system, collocate optimization procedure of design. It will increase sharing of hardware, and reduce complexity of hardware. Therefore achieve the goal of saving the area. At the same Finite Field GF(2^m), m=2~5, compare with other architectures. The proposed reduce a lot of area of hardware, and the number of clocks is fewer in latency. Then, we apply ones to RS decoder. Solve the problem that division is slow in calculation, improve whole performance. Finally, We implement the architectures using Verilog HDL and EDA design tool to produce the circuits of RS decoder.
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