| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 95 === This thesis is based on the utilization of the packet-based switch, to design and implement an efficient network on chip. Network on chip differentiates itself from the concept of ordinary on-chip bus, which uses a shared-bus structure to connect all the IP’s within a chip. The basic ideal of network on chip is to divide a traditional shared bus into several independent bus segments, and uses the switch to connect all IP’s. Thus, it can achieve greater bandwidth for improving multi-IP communication ability. Due to the differences in operating frequency among individual IP’s, the traditional shared bus structure design has difficulties in coordinating IP’s. However, Network on chip uses a network interface as a bridge between IP and switch for the flow control of packet data. With networking on chip, the whole system obtains globally asynchronous locally synchronous (GALS) attributes, making it easier to coordinate among IP’s with different operation frequency. Our proposed on–chip switch is a low hardware cost and low power consumption design, which uses a Mux-based Crossbar, and a fair arbitration controller. Flow control uses an independent hand shake mechanism, whereas, the routing mechanism makes use of a low hardware cost X-Y routing algorithm. The output port arbiter saves up to 49% on hardware usage, compared to the traditional Round-Robin arbiter, and 17% to the distributed arbiter. In delay time comparison, the output port arbiter reduces the time by 43% and 30% than the Round-Robin and distributed arbiters, respectively. Under the TSMC 0.13 processes, the on-chip switch can achieve an operating speed of 476MHz, with power consumption 12mW, and layout size of 0.15mm². A real chip is to be fabricated under the MPSoC-II project supported by CIC.
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