| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 95 === In this thesis, a low complexity complex QR factorization design suitable for signal detection in MIMO-OFDM systems is presented. Complex QR factorization is the essential processing block in various MIMO signal detection algorithms such as zero forcing, QR blast and sphere decoding. Conventional design approaches based on either Gram-Schmidt or Householder algorithms often lead to huge hardware complexity. In particular, most of the previous work are for real QR factorization. Recent complex QR factorization designs, nonetheless, suffer from long computing latency and low throughput rate, and thus can hardly meet the demanding computing requirement in MIMO applications nowadays. In this thesis, a novel low complexity QR factorization algorithm is first developed. The complex QR factorization problem of size N×M is first transformed into a real version counterpart of size 2N×2M. The proposed algorithm then exploit the symmetric property during the nullification process and effectively reduce the problem size to N×2M. Computing complexity analysis shows that the proposed scheme has lowest computing demands compared with those of the original complex algorithm and the conventional sized 2N×2M real algorithm. In architecture design, parallel CORDIC modules are employed to support concurrent vectoring and rotation operations. Via carefully planned pipelining and data flow control, our design can reduce the computing latency significantly to facilitate high throughput operations. In addition, no LUTs(Look-Up Tables) are needed as opposed to the conventional CORDIC implementation. In chip implementation, the design specs are mainly based on the 802.11n standard drafted by EWC (Enhanced Wireless Consortium). Implementing in TSMC 0.18um technology, the chip is capable of running at a top-notch speed 200.4MHz. It takes only 8 clock cycles to complete one 2×2 complex QR factorization with a minimum hardware cost of 16.26 K gate count only.
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