VLSI Design for Low Power and Low Cost Bypassing Multiplier
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 95 === In this paper, we proposed four novel low power multiplier designs based on improved row and column bypassing schemes. The basic idea is to eliminate unnecessary computation for power saving via signal bypassing. In an array multiplier, signal bypassing occu...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/19369867117928848000 |