Fast Extended Linear Scaling Algorithm for Digital Image and its 1D VLSI Architecture Design

• Main Authors: Zeng-chuan Wu, 吳曾傳
• Other Authors: Ming-hwa Sheu
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/48641786420416879566

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 95 === As multimedia applications become more popular and technology of manufacturing monitors progresses, more resolution specifications for digital displays are available now. Therefore, converting images to different resolutions while maintaining their high quality and low operation cost at the same time become a significant issue. This thesis presents two theoretical agendas for the study of image interpolation algorithm that is used during image scaling. First, an improved algorithm that bases on the classical bi-cubic interpolation is introduced to reduce its complexity of computation. By using this improved algorithm with the assumption that two-dimension interpolation can be decomposed to one-dimension calculation, a high efficient, low-cost and highly flexible circuit can be developed. Secondly, a new proposed image interpolation algorithm is used in conjunction with relevant theories in digital signal processing to demonstrate that it would not only achieve higher quality of image interpolation, lower operation and hardware cost but also be able to implement on the hardware architecture described above. To fully illustrate the proposed image interpolation algorithms and circuit architecture, FPGA and Prototype development platform are used to process prototype implementation of image scaling. The image scaling system which has real-time operation can be achieved by integrating the proposed interpolation circuit and related peripheral devices such as a CMOS sensor, SRAM and a VGA card. Finally, the image interpolation circuit is implemented onto a chip through the VLSI design flow and the chip is verified to meet the requirement of efficiency for most of the image specifications.