| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 95 === A fully differential active loop filter PLL-based frequency synthesizer which can generate a steady oscillating signal of 1.575GHz for GPS system is designed, in this thesis. The frequency synthesizer uses a quartz for oscillation at 24.61MHz as the reference signal; this signal then is used as the input of a phase-locked loop composed of a phase-frequency detector, a loop filter, a voltage-controlled oscillator, and a divider with division ratio of 64(N=64). When the loop converges, the VCO output signal frequency will equal 64 times of 24.61MHz. The synthesizer consists of a fast-acquisition phase-frequency detector, a differential charge pump, a fully differential active loop filter, a differentially Controlled Oscillator and a frequency divider with dynamic logic. A differential structure was chosen for better rejection of common-mode noise and overcome the noise from the supply and the substrate on high-frequency output signal. A good way to get rid of this source of mismatch is using active filter configuration to provide constant voltage at the outputs of charge pumps. The PFD possesses a wide linear-range in its characteristics and a high frequency-sensitivity. The frequency synthesizer is designed in the TSMC 0.18-µm CMOS process. The consumption power of the frequency synthesizer is 15.9mW with the 1.8V power supply. A wide range of VCO operation frequency, 1.02GHz-2.32GHz, is designed to ensure that the VCO still can generate the desired frequency even when the process conditions vary.
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