Design of A Dual Port Wave Pipelined Static Random Access Memory

• Main Authors: Wu Chin Chang, 吳錦昌
• Other Authors: 趙敦華
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/59059947880527436957

碩士 === 吳鳳技術學院 === 光機電暨材料研究所 === 95 === In this thesis, the design of a high speed static random access memory chip using dual-port wave-pipeline design method. This chip is designed according to the 0.35μm CMOS fabrication process rules. The distinguishing feature of our design is accomplished by adding two transistors to a 6T SRAM cell that makes a traditional memory unit equipped with two word-lines and two pairs of bit lines. A common SRAM memory unit is constrained by the fact that there is one pair of bit lines which can only be read/written once during one functional cycle. The access speed is therefore strongly limited and which is desired to be improved. The wave-pipeline designing method, although increasing the access throughput, only increases the access speed by little. Also presented in this thesis, the analysis of factors limits the access speed of a common SRAM and the dual-port wave-pipeline method is proposed to counteract the limiting bottleneck. This method allows two different memory cells can be accessed during each read or write cycle, therefore increases the access speed.