Effects of Boundary Conditions on Misalignment and Residual Stress for Flip Chip Bonding

• Main Authors: Sen-Hsiung Lo, 羅森雄
• Other Authors: C-H Chuang
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/43052177830322191042

碩士 === 南台科技大學 === 機械工程系 === 96 === Abstract Recently the demand for hand-held devices not only requires small size but also flexible property, which makes the amount of packaging IC on a flexible substrate rapidly increases nowadays. During the thermal cycle as packaging, the thermal expansion of flexible substrate could cause inner lead bonding (ILB) to fail due to the misalignment between gold bump and inner lead. Hence, in order to investigate the misalignment happened in realistic case, we introduced a new concept to simulate the boundary conditions as a flexible substrate fixed onto the heating stage for further ILB process. Instead of fixed-end boundary in the most ILB analysis, the differential pressure acting on the vacuum slot of heating stage was to represent the vacuum condition for stabilization of flexible substrate. By tuning the differential pressures and the positions of vacuum slot, the displacement of flexible substrate due to the vacuum force and thermal expansion was calculated to examine the accuracy of alignment. As the results from 2D model, out-of-plane displacements were affected by vacuum condition and happened near the vacuum slot, however, the difference between high and low vacuum is not much. On the other hand, the lateral displacements were governed by heat transfer and quite large in the 2D results, which means 2D model is not sufficient for representation of real case in the production line. For the 3D results, the displacements are all smaller than 2D cases due to the bi-directional constrain from 4-edge vacuum slots on the stage. Comparison of 3D results with misalignment error in the production line, the misalignment can be accurately predicted by finite element analysis here. In general, we provide a standard procedure to study the misalignment of ILB that can enhance the accuracy of compensation of the inner lead design for variety of chips.