| Summary: | 碩士 === 樹德科技大學 === 電腦與通訊研究所 === 95 === This thesis presents the design and implement a low power consumption for digital TV . The converter circuit uses flyback converter and sense feedback voltage. When the feedback voltage under 2.5V the PWM controller prevents oscillator frequency and output pulse.
Finally, We design an switching power supply with input voltage of 90Vac / 47Hz ~ 264Vac / 63Hz, Multiple output of +3.3V, +5V, +12V, +22V, +33V and maximum output power 20W, average efficiency of about 83.2%, Standby power consumption at input voltage 264Vac about 0.38W and meet EN55013 class B, FCC part 15 B EMI standard. Implement decrease energy consumption.
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