Research on Silicon Wafers Thinning and Planarization
博士 === 國立臺灣科技大學 === 機械工程系 === 95 === Wafer thinning and chemical mechanical planarization (CMP) process have been widely applied in integrated circuit (IC) fabrication. Due to demands of wafer production, backside thinning before IC packaging and reduction of line width in IC lithography, wafer thin...
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| Format: | Others |
| Language: | zh-TW |
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2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9rk9np |
| Summary: | 博士 === 國立臺灣科技大學 === 機械工程系 === 95 === Wafer thinning and chemical mechanical planarization (CMP) process have been widely applied in integrated circuit (IC) fabrication. Due to demands of wafer production, backside thinning before IC packaging and reduction of line width in IC lithography, wafer thinning and CMP can efficiently achieve the tight specification of thinning and planarization. This research aims to develop the wafer thinning model (WTM) to predict the total thickness variation (TTV) and also the wafer planarization model (WPM) to predict material removal rate (MRR) of wafers and multi-laminated heterogeneous film (MLHF). For wafer thinning, this research has developed the WTM with effective contact length (ECL). Simulated results of WTM show that the estimated TTV=0μm if the spindle tilting angles of chuck dressing and those of wafer grinding are the same values. Experimental results of TTV of 20 ground wafers can achieve 1-3μm with current set-up in this research. For wafer planarization, this research has developed WPM with the equivalent film thickness to simulate the material removal rate (MRR). Simulated results show that the numbers of abrasive and depth of cutting are significantly parameters on MRR. Comparison of the difference of MRR between simulated results and experimental results show that the numbers of abrasive, depth of cutting and hardness of pad are the main contribution of the prediction errors. Results of this study can be applied to large dimension wafer with the developed WTM and WPM. Further research is to explore in ultra-thin wafer grinding and also the CMP for IC fabrication under 90nm linewidth.
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