The Design and Verification of a System Coprocessor IP Compatible with ARM922T Architecture

• Main Authors: Hou-pin Su, 蘇侯斌
• Other Authors: Ming-Bo Lin
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/48605858082243078099

碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === In this thesis, a system coprocessor IP (Intellectual Property) compatible with ARM922T architecture, denoted as a Proto-ARM922 system coprocessor, is proposed. Through this coprocessor, the Proto-ARM9M microprocessor, a 16-KB cache memory, an MMU, and an AMBA bus interface are combined with the Proto-ARM922 processor into an integrated system. The datapath of the system coprocessor is a five-stage pipeline consisting of instruction decoder, register file, and handshake unit, and is used to control MMU, cache memory, and transferred data from/to Proto-ARM9M microprocessor through some dedicated instructions. The resulting system has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 μm cell library. In the FPGA part, it takes 12901 LUTs and operates at the maximum working frequency of 14 MHz. In the cell-based part, the core occupies 2580.48 μm × 2586.06 μm, which is approximately equivalent to 382854 gates, and the whole chip occupies 3250.92 μm × 3256.34 μm, and in the SS (Slow NMOS Slow PMOS model) simulation condition it operates at the maximum working frequency of 50 MHz.