Duty Cycle Corrector Based on Pulse Shrinking/Stretching Mechanism

• Main Authors: Shi-Wei Chen, 陳世崴
• Other Authors: Poki Chen
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/64732985219389742835

碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === The duty cycle correctors (DCCs) are widely used to adjust the clock duty cycle to 50% for DDR (double data rate)-SDRAM, double-sampling ADC, DLL (delay locked loop) and PLL (phase locked loop), where both clock rising and falling edges are used for operation. There are two major categories, digital and analog, for DCC realization in literatures. The digital DCCs can be further classified into the feedback type and the non-feedback type. The analog DCCs are usually implemented as feedback type to get better duty cycle accuracy at the expense of long locking time. In this thesis, a simple analog DCC with negative feedback is proposed. The pulse shrinking/stretching mechanism is utilized to achieve the duty cycle correction. Neither the complicated circuit in digital DCCs nor the charge pump in analog ones is required. A duty cycle corrector based on pulse shrinking/stretching mechanism is presented. The proposed DCC has been fabricated in a TSMC 0.35μm standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is between -1.0% to +1% for the widest frequency operation range of 3MHz~660MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 × 0.2 mm2 and the power consumption is 1.1mW at 550 MHz.