| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === As MOS devices are scaled down to the deep-submicron process, new reliability problems emerge. These include short-channel effect, hot-carrier effects, and gate-induced-drain leakage (GIDL). The tunneling field effect transistor (TFET) provides less short-channel effect, little hot-carrier effect, and little GIDL in high scaling fabrication. A band to band tunneling field effect transistor consists of n+-drain (source) and p+-source (drain). The electron-hole pairs are generated by band to band tunneling.
So far, some issues of TFET are still need to be resolved. In this study, further study of various device parameters for obtaining high-performance TFET is carried out via process and device simulation. This simulation was investigated with various parameters for obtaining high-performance TFET. These parameters include channel length (with various sidewall spacer length), substrate thickness, substrate doping concentration, gate oxide thickness, various drain biases, and substrate materials.
The performance of device is really improved by some parameters. For example, the on-current is increased by use of single crystalline SiGe substrate and off-current is reduced by a smaller drain biases. On the other hand, certain simulation indicates off-current is reduced and on-current is increased by certain ion-implantation profile and location.
Since there are not too many additional process steps compare with MOSFET, the TFET is an advancing device for low-power mobile applications fabricated with the standard CMOS process flow.
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