A NOR Emulation Strategy over NAND Flash Memory
碩士 === 國立臺灣大學 === 資訊網路與多媒體研究所 === 95 === This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobile phones. Different from LRU-related caching or buffering studies, we are interes...
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ndltd-TW-095NTU056410032015-12-07T04:04:00Z http://ndltd.ncl.edu.tw/handle/05920016816005235755 A NOR Emulation Strategy over NAND Flash Memory NAND型快閃記憶體上之NOR型快閃記憶體的模擬策略 Chien-Hung Lin 林建宏 碩士 國立臺灣大學 資訊網路與多媒體研究所 95 This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobile phones. Different from LRU-related caching or buffering studies, we are interested in prediction-based prefetching based on given execution traces of applications. An implementation strategy is proposed in the storage of the prefetching information with limited SRAM and run-time overheads. An efficient prediction procedure is presented based on information extracted from application executions to reduce the performance gap between NAND flash memory and NOR flash memory in reads. With the behavior of a target application extracted from a set of collected traces, we show that data access over NOR flash memory is responded effectively over SRAM that serves as a cache for NAND flash memory. Tei-Wei Kuo 郭大維 2007 學位論文 ; thesis 27 en_US |
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碩士 === 國立臺灣大學 === 資訊網路與多媒體研究所 === 95 === This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobile phones. Different from LRU-related caching or buffering studies, we are interested in prediction-based prefetching based on given execution traces of applications. An implementation strategy is proposed in the storage of the prefetching information with limited SRAM and run-time overheads. An efficient prediction procedure is presented based on information extracted from application executions to reduce the performance gap between NAND flash memory and NOR flash memory in reads. With the behavior of a target application extracted from a
set of collected traces, we show that data access over NOR flash memory is responded effectively over SRAM that serves as a cache for NAND flash memory.
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author2 |
Tei-Wei Kuo |
author_facet |
Tei-Wei Kuo Chien-Hung Lin 林建宏 |
author |
Chien-Hung Lin 林建宏 |
spellingShingle |
Chien-Hung Lin 林建宏 A NOR Emulation Strategy over NAND Flash Memory |
author_sort |
Chien-Hung Lin |
title |
A NOR Emulation Strategy over NAND Flash Memory |
title_short |
A NOR Emulation Strategy over NAND Flash Memory |
title_full |
A NOR Emulation Strategy over NAND Flash Memory |
title_fullStr |
A NOR Emulation Strategy over NAND Flash Memory |
title_full_unstemmed |
A NOR Emulation Strategy over NAND Flash Memory |
title_sort |
nor emulation strategy over nand flash memory |
publishDate |
2007 |
url |
http://ndltd.ncl.edu.tw/handle/05920016816005235755 |
work_keys_str_mv |
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