Effects of Electrostatic Discharge High-Field Current Impulse on Metal-Oxide-Semiconductor Devices

• Main Authors: Jen-Chou Tseng, 曾仁洲
• Other Authors: Jenn-Gwo Hwu
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/57756138998579700868

博士 === 國立臺灣大學 === 電機工程學研究所 === 95 === The effects of ESD high-field current impulse on gate oxide and made comparisons with the results of dc stress is studied in this thesis. Including generation of stress-induced trapped charges and the breakdown mechanisms were proposed. Besides, the density and spatial distribution of traps by ESD and dc stressing were investigated. According to the centroid of oxide trapped charges and the profile of interface traps induced by ESD stress, the explanation for locally filamentary current conduction and early oxide breakdown are suggested. Finally, lateral non-uniformities of border traps (near interface oxide traps) can lead to serious distortions of both C-V curve and charge-pumping signal, which may induce serious drift and degradation of the parameters of metal-oxide-semiconductor (MOS) devices. With respect to the formation of stress-induced traps in gate oxide, dc stress induces a large number of border traps and fast saturated positive oxide traps, whereas ESD stress generates less border traps and the increasing positive oxide traps. Under accumulation mode impulse stress, the positive oxide trapped charges can increase the applied electric field and deteriorate the oxide degradation during stressing, while border traps fail to de-trap charges and decrease the applied field near the interface and retard the oxide degradation due to the disabled response to the fast change of electric field. The effects between positive oxide traps and border traps on Fowler-Nordheim stress current are tradeoff during high frequency stress. Therefore, ESD emulation by TLP (transmission line pulsing) reveals a turn-around phenomenon of oxide breakdown characteristics under dc pre-stress. However, under TLP impulse pre-stress, the degradation continues increasing as the number of TLP pre-stress impulses increases. An impulse pre-stress thus appears to be a highly critical issue for the ESD immunity in devices and products. As for the breakdown mechanisms of oxide subjected to dc and ESD (TLP) stresses, it was iv observed that for 3.2-nm-thin oxide, the oxide trapped charges are generated by band-to-band impact ionization. The centroid evolution and the critical density of positive oxide trapped charges to trigger oxide breakdown are about the same and these results are consistent with the existing models of stress-induced trapping charges and the hole induced oxide breakdown. However, different behaviors of oxide trapped charges and centroid were found for 14-nm-thick oxides subjected to different stress tests. As compared with dc stress, which induces oxide trapped charges by trap-assisted impact ionization, the TLP impulse stress generates far less amount of oxide trapped charges by band-to-band impact ionization, and the positive oxide trapped charges finally dominates over the negative oxide trapped charges. This impulse stress imposes a high density and transient current on the oxide, induces traps at the tunneling distance locally. The hotter injected electrons generate more efficient hole trappings to provoke breakdown with lower density of oxide trapped charges. Regarding to the spatial distribution of interface traps in silicon dioxide induced by electrostatic discharge high-field current impulse. It was observed that TLP stress induces far less amount of interface traps prior to breakdown and the interface traps distribution along the channel direction is more non-uniform and localized than dc stress. The mechanisms are suggested that under ultra-high-field TLP stressing, the asperities at the electron injecting interface of gate oxide further increase the stress field locally, which enhances a regenerative avalanche process of impact ionization and trap generation. In addition, the lateral non-uniform distribution of trapped charges in stressed gate oxide was investigated. The distortions of low frequency C-V curves are mainly caused by the non-uniform distribution of border traps, which can be successfully simulated by the combination of C-V curves of heavily and lightly damaged regions. Besides, double-peak charge-pumping current is also observed in low frequency measurement. The non-uniform flat-band and threshold voltages are proposed as factors contributing to double-peak signal. And, devices with a shorter channel exhibit a more severe lateral non-uniform damage of gate oxide.