| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 95 === Abstract
Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) have been the trend of active matrix display driving circuitry, because of their high mobility, high aperture ratio, and the capability of integrating driver circuits into the panel frame. In the recent years, LTPS TFTs make a great strides by grown crystallize technology, Moreover, timer control circuit, source driver circuit, gate drive, level shift circuit and DC/DC convert circuit can be integrated on the glass substrate in the near future. How ever, the reliability issue and driving ability will be significant when the device sizes are scaled down.
In this thesis, the electrical characteristics, the current change of n-channel polycrystalline silicon thin-film transistors is analyzed experimentally and theoretically under different strain conditions, under the uniaxial strain parallel to the channel, the drain current will enhance, and the drain current will decrease on the uniaxial strain, recent year, strain enhance mobility technology has been extensively investigated for crystalline silicon, it has been attributed strain orientation and channel orientation, in low temperature poly silicon TFTs process, laser anneal induces crystalline has popularly used, after crystallization, silicon film will become poly silicon, and the inter grain orientation is depend grown temperature and crystallization method, and the TFTs are affected by strain.
In this thesis, negative and positive bias temperature instability of LTPS TFT have investigated, at first, the pMOS biased in high voltage induce hump issue, the threshold voltage will has a larger shift than negative bias stress, and the I-V curve will charge shape violent after short time positive bias stress, after stress, the hump will return to the origin condition slowly, but it can be accelerate by negative bias stress, in the experiment, we can explain the hump issue is caused by insulator thickness variation or fringe field, the high electronic field will induce external tuning current and generate more trap in device edge insulator.
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