Design and Implementation of 0.6-V CMOS Analog Circuits

• Main Authors: Chun-Hao Wei, 魏軍浩
• Other Authors: Liang-Hung Lu
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/92627528206084778623

碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === In the past decade, the fast growing market in consumer electronics has motivated the development of portable and hand-held devices with enhanced functionality and reduced fabrication cost. However, the battery lifetime required for the operation of such devices imposes a new challenge on the circuit designer. Provided the moderate advances in battery capacity, design techniques for low-power integrated circuits have attracted great attention. Besides, in consideration of the discharging curve of a battery, low-voltage circuit opera-tions are desirable such that more efficient usage of the battery power can be realized. Therefore, the topic of this thesis is mainly focused on low-voltage and low-power inte-grated circuit designs, and three circuits fabricated by TSMC 0.18-mm CMOS process are presented in this thesis. Firstly, a voltage regulator was designed to generate the supply vol-tage required to power the mixed-signal integrated circuits. By operating the transistors in the subthreshold region, the circuit provides a stable 0.6-V output voltage from an input voltage of 0.7 V. In addition, a Nyquist-rate ADC operating at 0.6-V supply voltage was implemented. By employing the redundant-signed-digit (RSD) algorithm and the proposed circuit technique, the non-ideal effects for low-voltage operations are thus alleviated. With a dc power consumption of 1 uW, the fabricated ADC achieves an ENOB of 6.8 bits. Finally, a 0.6-V Δ-Σ ADC is presented. Through the noise shaping property of Δ-Σ operation, various constraints imposed on the reduced supply voltage are eliminated. The ADC demonstrates a dynamic range of 57.5 dB at a dc power of 1.5 uW.