| Summary: | 博士 === 國立臺灣大學 === 電子工程學研究所 === 95 === To provide low-loss on-chip phase generations, monolithic transformers and a quadrature coupler are designed and implemented. The measured insertion losses of the transformers are below 2.5 dB over the band of interest. From 5.7 GHz to 5.9 GHz, the quadrature coupler exhibits phase errors of 1.3 ~ 4.8 degree, magnitude errors of 0.7 ~ 2.5 dB, side-band rejections of 17.0 ~ 24.1 dB and insertion losses of 3.6 ~ 4.2 dB.
The key part of this dissertation describes the design and the implementation of subharmonic-mixers (SHMs) along with experimental results showing that the proposed SHMs can prevent the LO-self-mixing DC-offset in direct-conversion receivers. The transformer-coupled configuration is incorporated into SHMs, where a step-up 1:4 transformer is used to contribute a voltage gain of 10.8 dB and achieve excellent linearity (IIP2 of 54.0 dBm and IIP3 of 7.9 dBm). The transformer-coupled SHMs are integrated with a band-variable low-noise-amplifier and the quadrature coupler to develop a 1.8-V receiver front-end.
The L-C folded-cascode topology is applied to both LNA and SHM so that a 1-V operation receiver front-end is successfully realized in 0.18-μm CMOS technology. At 5.4 GHz, the 1-V circuit exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred dc-offset due to LO self-mixing is below -110.7 dBm. By means of low-threshold-voltage transistors, a 0.5-V operation receiver front-end is also implemented with similar procedure. The 0.5-V circuit achieves 17.1-dB voltage gain and 8.7-dB noise figure at 5.6 GHz while consuming 19.4 mW from the 0.5-V voltage supply. The input-referred dynamic DC-offset is reduced down to –103.6 dBm. The quadrature generation of the 0.5-V receiver front-end is realized in the RF signal path with the quadrature coupler. The I/Q waveforms present 0.15-dB amplitude mismatch and 0.01° phase error at 5.6 GHz.
A miniaturized (0.224 mm2) 4.5~5.0 GHz area-efficient 3-D LC VCO with above-IC inductors is implemented. With inductors directly above the other devices, this VCO shows a measured phase noise of -124.6 dBc / Hz at 1 MHz offset from the 4.9 GHz carrier while dissipating 24 mW.
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