CMOS High-Speed Analog Key Components for Broadband Receivers

• Main Authors: Chihun Lee, 李志虹
• Other Authors: 劉深淵
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/00701825746384056864

博士 === 國立臺灣大學 === 電子工程學研究所 === 95 === Moore’s law has driven CMOS technologies toward broadband communication systems, which contains high-data-rate wireless communications (ISI/mm-Wave band and Radar), and high-capacity wireline communications (SONET/SDH, Fiber Channel, and Gigabit Ethernet). To realize Gb/s broadband transceivers, both front-end and clock generator play one of the critical roles. In this dissertation, CMOS high-speed analog key components for broadband receivers are presented. Even though III-V or bipolar processes had been widely used in 40Gb/s and 60GHz transceivers, they may have a large amount of power dissipation and make it difficult to fully integrate with the digital back-end. CMOS technology is to allow high levels of integration as well as low power and low cost. However, there are several problems in lossy CMOS, such as limited cut-off frequency fT, channel-length modulation, gate leakage, Miller effect, routing parasitic capacitance, substrate loss, limited supply voltage, etc. To resolve the above problems, several high-speed techniques are proposed, analyzed, and verified. First, a 35-Gb/s limiting amplifier (LA) in 0.13um CMOS is presented for wireline communications. It incorporates the cascaded distributed amplifier (CDA) with active-feedback and on-chip transformers to extend the gain-bandwidth product of active-feedback resistively-loaded amplifier by a factor of 5.2. The input offset-canceling stage and output broadband buffer are also described to improve the sensitivity and enlarge the amplitude. Second, a 60GHz frequency synthesizer in 90nm CMOS is presented for mm-wave communications. To accommodate the limited channel space for wireless applications, it requires a low reference frequency, therefore corrupting the performance of reference spur, settling time, and phase noise. Based on the proposed harmonic-locked technique, the divided frequency fdiv will lock with m times the frequency of fref. Resulting from the phase detector and dividers, in-band noise is attenuated by a factor of without the penalty of loop bandwidth. Compared with the PFD-type synthesizer, the proposed technique achieves a 57% reduction in settling time. Finally, a 57-77GHz mm-wave UWB receiver in 90nm CMOS is presented. To have a high-frequency clock generator, the proposed prescaler using merged-logic topology is needed. By using dual down-conversion approach, only one clock generator is needed to attain 60GHz/77GHz applications. For this purpose, the clock generator is proposed using different architectures: a quadruplicate-locked PLL and a ΔΣ fraction-N frequency synthesizer with the quantization noise shifting technique. The above key components facilitate the CMOS broadband realizations.