| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === As IC process geometries shrink to 65nm and below, the post-CMP dielectric thickness variation control becomes a dominant technique for manufacturability. To improve CMP quality and enhance the yield, layout uniformity is necessary. Dummy metal insertion is a general method to achieve layout uniformity in the post-routing stage. The post-CMP thickness would be affected by the variation and the gradient of metal density, which can be both minimized during the dummy insertion. However, inserting dummy features would increase coupling capacitance and timing delay. Thus, the coupling constraints need to be considered. In this thesis, we propose a dummy metal insertion algorithm considering gradient minimization and coupling constraints simultaneously. The framework contains coupling constraints regulation, multilevel dummy density analysis, and ILP-based fill synthesis with dummy number minimization. Experiments show that our method can achieve more balanced metal density distribution while using fewer dummy features, with an acceptable timing overhead.
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