Design and Implementation of Receiver Front-End Circuit for 10GBASE Optical Communication System

• Main Authors: Chao-Yung Wang, 王朝永
• Other Authors: Chorng-Kuang Wang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/90596186841901244244

碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === With the rapid growth in multimedia communication, the demand of high-speed data transmission is increasing. Optical communication systems are widely employed because fiber has many attractive advantages such as the high bandwidth and low sensitivity to interference, etc. In this system, transimpedance amplifier and limiting amplifier are two critical blocks of the receiver. Several designs of these circuits have been realized in III-V or SiGe bipolar technologies. However, CMOS technology is preferable candidate to achieve a low-cost solution due to its high integration characteristic. This thesis presents a transimpedance amplifier and a limiting amplifier for 10 GBASE-R Ethernet receiver. Both chips are implemented in 0.18-μm 1P6M CMOS technology. In the first design, two-stage transimpedance amplifier with inductive peaking is realized and the measured transimpedance gain is 59 dBΩ with the bandwidth of 8.6 GHz. It consumes 18 mW from a 1.8-V power supply and the chip occupies an area of 0.61 x 0.68 mm2. For the second work, limiting amplifier employs active feedback architecture to increase the gain-bandwidth product of the circuit. In addition, negative capacitance technique is applied to enhance the bandwidth and reduce the chip area. According to post-layout simulations, the gain of the limiting amplifier is 41.5 dB and the bandwidth is 800 kHz ~ 8 GHz. The chip area of core amplifier is only 0.3 x 0.57 mm2 and it consumes 120 mW from 1.8-V power supply.