High-Level Design Intent Extraction for Intelligent Verification
碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === High-level design intents such as finite state machine (FSM) and counter are commonly used in modern VLSI design. We can use them to guide the exploration of the design space and thus improve the verification efficiency. However, previous works on high-level int...
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| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86540330488176707571 |