High-Level Design Intent Extraction for Intelligent Verification

• Main Authors: Chi-Wen Chang, 張啟文
• Other Authors: Chung-Yang( Ric ) Huang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/86540330488176707571

碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === High-level design intents such as finite state machine (FSM) and counter are commonly used in modern VLSI design. We can use them to guide the exploration of the design space and thus improve the verification efficiency. However, previous works on high-level intent extraction can only identify very limited constructs such as explicit FSM in restricted coding style. In this work, we propose a novel technique which can extract all the explicit, implicit FSMs and the counter. We also prove with several theorems that our algorithms are very robust and not limited to the coding styles and the HDL synthesizable subset. The experimental results on several real designs demonstrate that our program is superior over existing commercial tools.