Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes
碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === A frequency synthesizer plays an important role in wireless communication systems. Both transmitter and receiver need the synthesizer to generate local oscillation frequency. In addition, a transmitter can be implemented by utilizing the in-loop modulation of a...
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ndltd-TW-095NTU054280022015-12-11T04:04:49Z http://ndltd.ncl.edu.tw/handle/89934189088311594502 Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes 除小數頻率合成器之應用與效能改善;實現雙點調變發射機及增進線性化技巧 Ching-Lung Ti 狄敬隆 碩士 國立臺灣大學 電子工程學研究所 95 A frequency synthesizer plays an important role in wireless communication systems. Both transmitter and receiver need the synthesizer to generate local oscillation frequency. In addition, a transmitter can be implemented by utilizing the in-loop modulation of a phase-locked loop (PLL) based frequency synthesizer. This thesis is separated into two parts, transmitter implementation and synthesizer performance improvement, respectively. Before entering the two main sections, the fundamentals of a PLL were introduced first. The analysis, modeling, and a phase domain model are provided for quick simulation and parameters determination. In the implementation of a transmitter, a scheme called “Two-Point Modulation” is employed for in-loop modulation of a fractional-N PLL. With this technique, a transmitter suitable for IEEE 802.15.4 standard in 2.4-GHz ISM-band application is designed, implemented, and measured. The measured power consumption is 18 mW under a 1.4-V supply voltage, and the achievable data rate is higher than 2 Mbps. In the second part, three linearization techniques are introduced. A dynamic current-balancing charge pump, a gated-offset current scheme, and an unbalanced reset delay phase frequency detector (PFD) are introduced. The reasons of stringent linearity requirements are described, and the effects of nonlinearities on PLL performance are simulated. With theoretical analysis, the simulated and measured results agree with the hand-calculated results. With a 1-MHz wide loop bandwidth and a 20-MHz reference frequency, the new charge pump circuit achieves below -60 dBc reference spur with small-sized area. The gated-offset current obtains about 8-dB improvement with 10-% offset current applied to the PLL system. The new PFD realizes the shifting of operation region without additional current sources. Tsung-Hsien Lin 林宗賢 2007 學位論文 ; thesis 90 en_US |
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碩士 === 國立臺灣大學 === 電子工程學研究所 === 95 === A frequency synthesizer plays an important role in wireless communication systems. Both transmitter and receiver need the synthesizer to generate local oscillation frequency. In addition, a transmitter can be implemented by utilizing the in-loop modulation of a phase-locked loop (PLL) based frequency synthesizer. This thesis is separated into two parts, transmitter implementation and synthesizer performance improvement, respectively. Before entering the two main sections, the fundamentals of a PLL were introduced first. The analysis, modeling, and a phase domain model are provided for quick simulation and parameters determination.
In the implementation of a transmitter, a scheme called “Two-Point Modulation” is employed for in-loop modulation of a fractional-N PLL. With this technique, a transmitter suitable for IEEE 802.15.4 standard in 2.4-GHz ISM-band application is designed, implemented, and measured. The measured power consumption is 18 mW under a 1.4-V supply voltage, and the achievable data rate is higher than 2 Mbps.
In the second part, three linearization techniques are introduced. A dynamic current-balancing charge pump, a gated-offset current scheme, and an unbalanced reset delay phase frequency detector (PFD) are introduced. The reasons of stringent linearity requirements are described, and the effects of nonlinearities on PLL performance are simulated. With theoretical analysis, the simulated and measured results agree with the hand-calculated results. With a 1-MHz wide loop bandwidth and a 20-MHz reference frequency, the new charge pump circuit achieves below -60 dBc reference spur with small-sized area. The gated-offset current obtains about 8-dB improvement with 10-% offset current applied to the PLL system. The new PFD realizes the shifting of operation region without additional current sources.
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author2 |
Tsung-Hsien Lin |
author_facet |
Tsung-Hsien Lin Ching-Lung Ti 狄敬隆 |
author |
Ching-Lung Ti 狄敬隆 |
spellingShingle |
Ching-Lung Ti 狄敬隆 Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes |
author_sort |
Ching-Lung Ti |
title |
Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes |
title_short |
Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes |
title_full |
Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes |
title_fullStr |
Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes |
title_full_unstemmed |
Application and Improvement of Fractional-N PLLs; Two-Point Modulation Transmitter and Linearization Schemes |
title_sort |
application and improvement of fractional-n plls; two-point modulation transmitter and linearization schemes |
publishDate |
2007 |
url |
http://ndltd.ncl.edu.tw/handle/89934189088311594502 |
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