networks on chip generation and synthesis for system-on-a-chip

• Main Authors: Der-Tzeng Tsai, 蔡德政
• Other Authors: Mong-Kai Ku
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/11388209170274007661

碩士 === 臺灣大學 === 資訊工程學研究所 === 95 === Networks-on-chip (NOC) has been proposed as a promising solution to complex on-chip communication problem. It is used to overcome the communication and the performance bottlenecks of bus based interconnection. NOC architecture consists of a collection of intellectual property (IP) cores interconnected by on-chip routers. Since an application-specific NOC for one SOC design can not be re-applied to another SOC design, it is essential to devise a tool for generating fast and efficient NOC. In this work, we propose a tool that generates application-specific networks-on-chip automatically by giving application description files and connection files. We also design the components of NOC including routers and network interfaces. We focus on a mesh-based topology and packet switching NOC. We present a fast algorithm for mapping cores onto a mesh-based NOC, minimizing the communication delay. Compared with other work, simulation results with two benchmarks make significant savings on communication cost by using our tool. This tool is applied to AES-RS codec and LDPC decoder. All results are verified on Alter''a FPGAs.