Low Power Mapping of Cores onto Hybrid Noc Architectures

• Main Authors: Jhih-De Wang, 王志得
• Other Authors: Fei-Pei Lai
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/25427377363483077617

碩士 === 臺灣大學 === 資訊工程學研究所 === 95 === With the advance of the semiconductor technology, a huge number of transistors available on a single chip allows designers to integrate tens of intellectual property (IP) blocks together with large amounts of embedded memory. In tradition, data was transferred with bus based on shared medium architectures. However, the bus based on shared medium architectures will not be suitable as they will have to be implemented as hierarchical structures extending to multiple levels. SoC would face the problems like the huge power consumption caused by the complicated bus, the high signal propagation delays which would make synchronous bus based global communication difficult, and also the noise due to the increased RLC effects in deep sub-micro technologies. The NoC (Network-on-Chip) architecture was recently proposed to overcome limitations of the bus architecture. A NoC is an intra-chip communication infrastructure and usually composed by a set of routers inter-connected by point to point communication channels. Even many methods designing the NoC have been proposed which overcome many problems of the SoC, however, there are some new problems emerging. For examples, Quality of Service (QoS), bandwidth optimization, switch design, and Network Interface (NI) design are the points we need to focus on as we design NoC. In this thesis, we discuss two issues, the first one is that we propose a new intelligent architecture combining the SoC and the NoC these two architectures together, and another one is that we propose a solution to the problem of mapping applications onto our architecture while considering execution time and energy consumption.