Embedded a CORDIC Processing in MIPS CPU Design

• Main Author: 胡登貴
• Other Authors: 張吉正
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/47709683361758521616

碩士 === 國立臺灣師範大學 === 機電科技研究所 === 95 === This thesis is a study of embedding the CORDIC(COodinate Rotation DIgital Computer) algorithm into MIPS CPU design. Finally, a 32-bit MIPS CPU with trigonometric arithmetic instructions as well as a floating-point co-processor was implemented. The final design had been tested and simulated by ModelSim and verified by downloading into Xilinx Virtex XCV800 FPGA(Field Programmable Gate Array) successfully. The CORDIC algorithm had been utilized in many DSP applications recently because of its fast computation and simple hardware structure. The cooperation of a microcontroller and a DSP processor could be used in many DSP applications, but this thesis provides an alternation of embedding the CORDIC algorithm into MIPS CPU. We hope this combination will be more suitable in some simple applications, (like one may need only a few DSP instructions,) and achieves cost-down by this way. In this thesis, there are 37 fixed-point, 4 floating-point and 2 trigonometric(Cos and Sin) instructions, 43 instructions have been implemented totally.