Detection of stress-induced Interface Traps and Border Traps in MOSFETs with High-K Gate Dielectrics

• Main Authors: Chun-Chang Lu, 呂君章
• Other Authors: Kuei-Shu Chang-Liao
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/35641987665485802149

碩士 === 國立清華大學 === 工程與系統科學系 === 95 === Abstract To fulfill the scaling scenario as projected in the International Technology Roadmap for Semiconductors (ITRS), it is widely believed that a high-k (high permittivity) dielectric is needed to replace SiO2 as the CMOS gate dielectric to reduce significantly the gate leakage current. With the using of these alternative materials, the analyses of interface and gate dielectric quality have become important due to the higher interface states and worse gate dielectric quality. The interface states can trap electrons or holes and even the border traps can also. Trapped charge causes instabilities of electrical properties like threshold voltage shift, carrier mobility degradation and less reliability. Hence, the studies of the interface states and depth profile of border traps and trapping mechanism play a significant role in the new generation semiconductor industry. In this work, we applied charge pumping technique to reliability measurement. Experimental results indicate that the weak bonds present in high-k gate dielectric are easily trapped by charges after stress; thus, stress results in a large Vth shift. It is also demonstrated from the Nbt profile that the border trap induced by stress is probably not a fixed trapping center but a mobile defect like hole. Moreover, we discuss the tunneling component of CP current and effects of voltage swing in high-k gated MOSFETs. An effective method was proposed to eliminate the tunneling component. Finally, the limitation factor of Nbt(x) depth profile measurement was investigated. We should carefully set voltage swing and bias level to choose electron or hole as limitation factor.