Built-In Speed Grading with a Process-Tolerant All-Digital Phase-Locked Loop

• Main Authors: Chun-Chieh Tu, 涂竣傑
• Other Authors: Shi-Yu Huang
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/08780456070459777084

碩士 === 國立清華大學 === 電機工程學系 === 95 === Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry. This Built-In Speed Grading (BISG) methodology uses an All-Digital Phase-Locked Loop (ADPLL) as the programmable clock generator to provide various clock signals within a specific frequency range. The maximum operating speed of a circuit can thus be easily tracked down using a binary search process with multiple runs of built-in self-test. To accommodate larger process variation, we further explore a so-called binary-neighborhood-linear frequency-locking scheme for the underlying ADPLL, and thereby resulting in a higher accuracy. Experimental results show that only 2289 gates are adequate to provide this valuable infrastructure that may find numerous applications in IC testing and diagnostics.