| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 95 === For high speed network transmission, the high speed low power multiplexer is more important in I/O interface. The main function of the multiplexer is to serialize many parallel buses into a serial link. To overcome the DC balance problem during data transmission, the 8B/10B encoder is often used for network transmission. The 16/20:1 multiplexer can do two bytes serialization at the same time for the data encoded or not.
In this thesis, a quarter-rate 16/20:1 multiplexer mixed with the tree-based type and the shift-register type is proposed. The operation frequency of most blocks is only one-fourth to the output data rate. That makes the circuit more easily to design, more stable and lower power consumption. For those low speed blocks, the full swing TSPC registers are used. Its noise tolerance is better and the power dissipation is reduces. For the high speed blocks, the differential type current mode logic (CML) is adopted. This architecture achieves better balance among the speed, stability and power dissipation.
For the design of high speed circuits, the study at device level is very important besides the architecture. TSMC provides two devices: the RF device and the baseband device. The RF device is suitable for high speed circuits, its noise shielding is better with the drawback of huge area consumption. The baseband device is good for low speed circuits; smaller area is the advantage. This thesis studies these devices in detail, and proposes the area-saving RF device with lower area consumption. The area-
saving RF device reserves the advantage of the RF device with good performance at high speed operation and good noise shielding; furthermore, the area is reduced.
Two quarter-rate 16/20:1 multiplexers are proposed in this thesis. One is based on the TSMC 0.18um technology; all transistors are the area-saving RF devices. It can achieve the 6Gbps data rate with 10 picoseconds jitter. The other is based on the TSMC 0.13um technology; the architecture is mixed with the area-saving RF devices and the baseband devices to reduce the area. Its maximum data rate is 8.8Gbps with 18 picoseconds jitter. The area is only 23.2% to that with all area-saving RF devices.
The multiplexer designed with 0.18um technology is integrated into a SERDES chip. The measurement result shows that it can achieve 5.12Gbps data rate. For that with 0.13um technology, it is integrated into a 4 x 4 STDM Switch IC. Based on the post-simulation result, the maximum speed can achieve 7Gbps data rate. Overall speed is 28Gbps / 4ch.
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