Quarter-Rate 1:16/20 Demultiplexer for High Speed Switch Fabric Application

• Main Authors: Ming-Hao Lu, 盧明豪
• Other Authors: YarSun Hsu
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/26247108820396159187

碩士 === 國立清華大學 === 電機工程學系 === 95 === As the optical communication and network technology improve, the required transmission data rate also increase gigabit-per-second range. High speed I/O interface design becomes an important issue. In the recent year, serial link transmission method is extensively used in high speed communication. The serializer/deserializer (SerDes) interface plays an important in serial link transmission. The multiplexer converts the low-speed parallel data bus into a high-speed serial data stream and transmits the serial data stream out. On the contrary, the demultiplexer receives the high-speed data stream and converts the data stream into low-speed data bus. By using the SerDes interface, we can easily increase the overall circuit bandwidth without increasing the pin count. The system scalability is also improved. We employ the SerDes interface in the load-balanced Birkhoff-van Neumann switch fabric design to build up a high speed network switching system. In this thesis, we focus on the design and implementation of the quarter-rate 1:16/20 demultiplexer. We propose new quarter-rate architecture to realize the 1:16/20 dual-mode demultiplexer. The quarter-rate architecture relaxes the loading of the high frequency clock signal and the circuit operating at quarter-rate speed would work more stable. The quarter-rate architecture combines the binary tree type and multiple-phase sampling architecture to achieve the non-power-of-two demultiplexer function. The CML and TSPC circuits are employed in the 1:16/20 demultiplexer design for high speed consideration. The quarter-rate 1:16/20 demultiplexer design is realized in TSMC 0.18μm and 0.13μm CMOS technology. In 0.18μm demultiplexer design, the whole circuits are implemented by the RF model device to improve high frequency operation performance. We integrate the 1:16/20 demultiplexer in the one-channel SerDes interface. The total area of the SerDes is 2.49mm × 2.49mm. In the chip measurement, the one-channel SerDes interface can work up to 5.12Gbps data rate. In 0.13μm demultiplexer, we use the same architecture to implement the 1:16/20 demultiplexer but do several changes. We mix the RF and baseband model device in the 1:16/20 demultiplexer implementation and the circuit area can be reduced. The area consumption of the 0.13μm demultiplexer is only 30% of the 0.18μm design. The 1:16/20 demultiplexer is integrated in the 4 × 4 load-balanced switch fabric. The 4 × 4 load-balanced switch fabric consists of the digital switch core circuit and quad SerDes interface. The grounded coplanar waveguide (GCPW) type transmission line is employed to reduce the clock tree skew for the quad SerDes to within 1ps. The total area of the 4 × 4 load-balanced switch fabric circuit is 3mm × 2.48mm. We have verified that each SerDes interface can work up to 7Gbps in the quad SerDes interface. Therefore, we can estimate that the maximum throughput of the 4 × 4 switch fabric is about 28Gbps.