LCD Pixel Rate Clock Generator

• Main Authors: Yu-Chun Wang, 王宇淳
• Other Authors: Po-Chiun Huang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/58816019899386083905

碩士 === 國立清華大學 === 電機工程學系 === 95 === In a LCD system, a frequency synthesizer with high multiplying ratio is required to sample the analog RGB data from graphic card on PC. The reference clock is a jittered clock, HSYNC. Since the RGB data is phase aligned with the HSYNC, the synthesized pixel rate clock should track the timing variation of the HSYNC. Existing closed loop topologies of frequency synthesizers are not able to track the variation of the HSYNC very fast due to their loop bandwidths. An open loop architecture, whose core is a DDFS, is proposed and analyzed in this thesis. System simulation shows the feasibility of this architecture. Key circuits were implemented using 0.18um CMOS technology. Measured results of prototyping system show the jitter performance of the modified pixel rate clock.