Analysis of High Frequency Noise in Advanced MOS Transistors

• Main Authors: Hsin-Yi Yang, 楊欣逸
• Other Authors: Shuo-Hung Hsu
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/69874705189590071652

碩士 === 國立清華大學 === 電子工程研究所 === 95 === With technology progressing continuously, MOSFETs are utilized extensively in high frequency applications. As the device size scaling down, the analysis of high frequency noise becomes more complicated than that in the conventional long channel devices. Many publications have studied the excess thermal noise and derived the analytical equations from different models. Although the final proposed equations are different, some similar effects such as velocity saturation, channel length modulation and so forth are adopted. In this study, we set a simple procedure to cope with the experimental data and verify those equations by using standard 0.13-�慆 and 0.18-�慆 devices, inclusive of n- and p-channel MOSFETs. Furthermore, we focus on the analysis of the four noise parameters, and observe the similarities and differences of these parameters as functions of both the frequency and bias voltage. Such as biasing adequate voltage corresponding to different devices can achieve their optimized performance. At last, the waffle-type layout MOSFET which is expected to possess lower high frequency noise has been designed. We investigate the high frequency noise characteristics with different device layouts. The waffle configuration reduces its channel thermal noise compared with multi-finger type about 30-47% at different frequencies and bias voltages. The noise resistance is also decreased by 9%. Moreover, the gates of waffle device can be connected on both sides to reduce gate resistance to improve its noise performance.