| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 95 === Clock and data recovery circuits (CDR) have already been applied in a lot of consumption electronic products. The ones that applied to serial data communications, under the circumstances that lower data rate, CDR circuits are usually realized by digital circuits, such as digital type phase-locked loop (DPLL). On some high-speed applications, such as optical fiber communication systems, because the data rate is relatively high, so CDR circuits are usually implemented by analog circuits. For transceivers which reach Gb/s are usually realized by GaAs, SiGe, BJT and BiCMOS, because their operate frequency can be relatively high, and have better immunity for noise. But they usually spend large power consumption, beside are expensive and not suitable for integration. In recent years, the CMOS technologies progress constantly, so CMOS CDR is used and issued far and wide at the academic periodical. Because CDR circuits are often needed for integrated with other circuits, so CMOS which is low power consumptive, low cost and high integrating is very suitable for reaching the goal of SOC.
A 2.5Gb/s half-rate CDR circuit for SONET OC-48 application is presented in this thesis, including half-rate phase detector, half-rate frequency detector, charge pump, loop filter and voltage-controlled oscillator. Under the half-rate architecture, the frequency of voltage-controlled oscillator must operate in 1.25GHz, therefore we reduce the design difficulty of voltage-controlled oscillator. We hope that the CDR circuit can be realized by TSMC 0.35μm 2P4M CMOS process which is cheap and high integration to reach high-speed and high-capability applications. Simulation results show that this CDR circuit operating under 3.3V, the power consumption is 107.7mW (without I/O buffers).Measurement results show that the CDR circuit can lock under periodic 2.5Gb/s data, and the chip size is 1160 x 980μm2.
|
|---|
