Statistical Analysis for Failure-Pattern Based Memory Failure Diagnostics
碩士 === 國立清華大學 === 產業研發碩士積體電路設計專班 === 95 === According to the recent ITRS report, memory cores will occupy more than 90% of the chip area in just a few years. The design of embedded memory test has became an essential part of SOC development infrastructure. Failure analysis (FA) and memory diagnostic...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67242355719850852813 |