| Summary: | 碩士 === 國立清華大學 === 產業研發碩士積體電路設計專班 === 95 === According to the recent ITRS report, memory cores will occupy more than 90% of the chip area
in just a few years. The design of embedded memory test has became an essential part of SOC
development infrastructure. Failure analysis (FA) and memory diagnostics play important roles in
SOC product development and yield ramp up. Conventional FA, like physical analysis, is timeconsuming
and expensive. Compared with physical analysis, the analysis based on failure pattern
is more acceptable and simple. To improve yield in new process flow, we need an efficient and
automatic methodology such as repair technique with redundant element or memory diagnostics.
In this thesis, we propose a failure pattern oriented memory diagnostics methodology based on
failure pattern statistics.
In order to analyze the failure patterns, we developed some tools—physical bitmap convertor
and failure pattern extractor (FPE)–help to convert bitmaps and extract failure patterns. We can
verify the result with the failure pattern viewer that was developed by our laboratory previously,
and we can identify the failure pattern which is special or appear frequently. The FPE provides the
failure pattern statistics and sufficient failure information such as the faulty cell count of each bit
line (BL) failure pattern, and the distribution of failure pattern after execution. This information
is helpful for redundant element and repair circuit design. This complete, detailed information is
also useful in the Redundancy Analysis (RA). In addition, we can use the failure pattern to narrow
down the potential cause of failures and identify possible defects with the defect dictionary on
wafer level. An experiment has been done on an industrial case, and the demonstrated results are
reasonable.
Our proposed approach provides another efficient way for memory diagnostics, and constructs
a model of realistic failure distribution. This information of realistic failure distribution can help us
to point out the key reason of the yield loss efficiently. The information of failure pattern generated
can be used to diagnose memory on wafer level. This work has been very helpful in redundancy analysis and memory diagnostics during memory product and yield improvement.
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