Design and Implementation of Real-Time Block-Based Gradient Domain High Dynamic Range Compression
碩士 === 國立清華大學 === 產業研發碩士積體電路設計專班 === 95 === Due to rapid progress in high dynamic range (HDR) capture technology, HDR images or video display on conventional LCD devices becomes an important topic. Tone mapping algorithms are proposed for rendering HDR images on conventional displays. However, they...
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| Format: | Others |
| Language: | en_US |
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2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14414370735335066963 |
| Summary: | 碩士 === 國立清華大學 === 產業研發碩士積體電路設計專班 === 95 === Due to rapid progress in high dynamic range (HDR) capture technology, HDR images or video display on conventional LCD devices becomes an important topic. Tone mapping algorithms are proposed for rendering HDR images on conventional displays. However, they are impractical for video applications due to intensive computation time. In this paper, we present a real-time block-based gradient domain HDR compression for image or video applications. The gradient domain HDR compression is selected as our tone mapping scheme for its ability of high compression and detail preservation. We equally divide one HDR image/frame into several blocks and process each block by the modified gradient domain HDR compression. The gradients of small magnitude are attenuated less in each block to maintain the local contrast and thus expose the detail. We reconstruct a low dynamic range image by solving the Poisson equation on the attenuated gradient field block by block. A real time DST architecture is proposed to solve the Poisson equation. We implement the hardware of real-time block-based gradient domain HDR compression by Verilog HDL. Our synthesis results show that our hardware architecture for HDR compression with DST Poisson solver can run at 50MHz clock and consume area of 14 mm2 under TSMC 0.13um technology and the power consumption of the design is 43.67mw.
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