Construct Two-Phase Decision Tree for Chip Size Optimization to Empower Design for Manufacturing

• Main Authors: Chia-Chih Liu, 劉家志
• Other Authors: Chen-Fu Chien
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/56471379631843058749

碩士 === 國立清華大學 === 工業工程與工程管理學系 === 95 === In order to enhance the competitive advantages of wafer fabs, it is crucial for wafer fabs to increase the number of gross dies per wafer to reduce average die cost through productivity improvement. However, gross die number is influenced by die size in design phase, while the existing size of integrated circuit die was designed without considering the effect on wafer throughput in fabrication phase. This research aims to bridge the gap between design and wafer exposure by providing design advice with optimal feature size of integrated circuit device in the design phase so as to improve the overall wafer effectiveness in fabrication. In particular, a two-phase decision tree algorithm for die size optimization is developed to construct the rules between the numbers of gross dies per wafer and mask utilization to the die feature including length, width, and area. Without losing generality, an empirical study has been done for validation by using transformed data from a fab in Taiwan. The results show practical viability, in which the IC designer can easily use these extracted rules to design optimal integrated circuit die size for maximizing the gross die number per wafer and reducing the fabrication cost at the same time.