| Summary: | 碩士 === 國立清華大學 === 工業工程與工程管理學系 === 95 === In recent years, new technologies have been designed in semiconductor fabrication and led to design delicate electronic product widely used by public in application purpose. Moreover, new technologies make electronic industry a skyrocket and one of the most important industries. Due to the complexity of semiconductor manufacturing, engineers make efforts to trace causes of chip malfunctions during the process, and the analysis of correlations between WAT parameters and Bin values are one of the promising approaches to find out the root causes.. The relation between them is very complicated due to the complex fabrication and therefore, engineer can not find out the problem in a short time. This research focus on the analysis of relationship between abnormal procedure and WAT parameters. A Decision Tree algorithm is presented to analyze abnormal wafer lots in batch mode to find out valuable information, and then collects relative traits of WAT parameters to realize the relationship between Bin values and WAT parameters. Thereafter, specific WAT parameters that may cause bad Bin values under certain situations can be determined and then engineers can be able to monitor and diagnose following manufacturing process. This research collects 50 samples of wafers for the analysis. The experiment results show the accuracy of presented approach is 84.65.With the extraction method of the relation trait introduced by this research, we can effectively find out the complex relation between yield and WAT parameters and provide some useful information for engineer for further monitoring and yield improvement.
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