Performance Evaluation of Data Access Latency Hiding Techniques in Processor Design

• Main Authors: Jia-hao Jhang, 張家豪
• Other Authors: Tsung Lee
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/h7d9ep

碩士 === 國立中山大學 === 電機工程學系研究所 === 95 === Due to the effect of deep submicron technology, the gap between processor speed and memory access performance increases continuingly. In order to improve performance degradation due to the performance gap, one way is to fetch the data about to be accessed by processor to buffer memory on the processor chip in advance. The memory access waiting time can thus reduced between main memory and cache memory on the processor. Previous research utilizes low-level techniques to pre-fetch data, such as insertion of pre-fetch instructions and pre-fetch with predicted data location based on dynamic learning. They do not utilize analysis on program’s high-level data structure to assist data pre-fetch. In this research, we carried out performance evaluation on our proposed data pre-fetch technique based on analysis of high-level data structures. We also compare our method with some existing low-level data pre-fetch techniques. The evaluation metrics includes the accuracy of data pre-fetches, memory latency hiding, and overall execution performance.