| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 95 === Reconfiguration systems use the partial reconfiguration characteristic of FPGA to dynamically load different bitstreams into different partial reconfiguration regions without affecting other active circuit areas. The hardware must provide two functions to support dynamic reconfiguration. First, the FPGA must support the partial reconfiguration function. Many Xilinx FPGAs such as Virtex-II and Virtex-IV have supported the function. Second, the FPGA must provide a way to load a partial bitstream into a specific region during the runtime. This can be achieved through the Xilinx Internal Configuration Access Port (ICAP).
However, the functions mentioned above are not sufficient for constructing a dynamic self-reconfiguration system. In this paper, we describe the design flow and the related hardware support for constructing such a system based on the aforementioned hardware functions. We have also implemented the system and the hardware support. In our system, partial bitstreams that were stored in the external flash memory can be loaded into one of the four reconfiguration regions on demand. Moreover, a static module in the system is used for communication between the processor (i.e., Microblaze) and the dynamically-loaded hardware. The static module communicates with Microblaze via FSL (Fast Simplex Link), and communicates with all the dynamically-loaded hardware modules via a uniform interface defined by us. According to the experimental results, configuring a floating-point square-root bitstream via ICAP requires only 0.696 second, which is acceptable in common cases.
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