Investigation and Logic Application of InGaP/InGaAsDoped-Channel High Electron MobilityField-Effect Transistors

• Main Authors: Tzu-Yen Weng, 翁子晏
• Other Authors: Jung-Hui Tsai
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/37352121710286230212

碩士 === 國立高雄師範大學 === 物理學系 === 95 === In this thesis, based on InGaP/InGaAs doped-channel pseudomorphic heterostructure field-effect transistors (HFETs), novel integrated enhancement/depletion-mode devices are addressed. The devices could exhibit high gate barrier, high turn-on voltage, high linearly transconductance, lower saturation voltage, broad gate voltage swing, and excellent high frequency performance. Furthermore the relatively large noise margins are achieved in direct-coupled field-effect transistor logic (DCFL) application. The simulation tool silvaco is used to simulate the performances of the InGaP/InGaAs doped-channel high electron mobility field-effect transistors (DC-HEMTs). First, the InGaP/InGaAs integrated enhancement/depletion DC-HEMTs on the identical chip are first demonstrated. Due to the higher electron mobility, higher peak electron velocity and lower effective mass of InGaAs material, it is favorable to use an InGaAs to replace the GaAs as a channel layer to improve the device performances. As to the depletion-mode device, the upper doped-channel layer is entirely depleted and the depletion region is justly immersed into the lower doped-channel layer at equilibrium .It forms subband and two-dimensional electron gas (2DEG) in the low InGaAs strain channel, which increase the channel concentration. On the other hand, for the enhancement-mode device the doped-channel layer is completely depleted at equilibrium and the active channel appear under sufficient large gate forward bias. Second, the monolithic integration of enhancement and depletion-mode FETs in the same chip provides the reduction of fabrication complexity by the implement of inverters. The power supply voltage can be effectively reduced resulting from the low drain-to-source (D-S) saturation voltage. The integrated DC-HEMTs exhibit the larger noise margins than the HEMTs for DCFL application because the saturation voltages of the integrated device are relatively small.