SPICE Modeling for Phase Change Memory Element
碩士 === 國立宜蘭大學 === 電子工程學系碩士班 === 95 === Continuous scaling of the memory device has been a challenging task. Phase change memory (PCM) is a potential candidate for next generation non-volatile memory. The advantages of PCM including better scalability, rewritability, high speed which facilitate devic...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/46602274971114523668 |
| Summary: | 碩士 === 國立宜蘭大學 === 電子工程學系碩士班 === 95 === Continuous scaling of the memory device has been a challenging task. Phase change memory (PCM) is a potential candidate for next generation non-volatile memory. The advantages of PCM including better scalability, rewritability, high speed which facilitate device scaling. In this thesis, we developed a PCM model for SPICE with Verilig-A. The material of PCM is based on Ge2Sb2Te5 (GST). Different current pulse width and amplitude can generate different temperature in the cell; it will change the phase of GST between crystalline and amorphous and hence can store the data. We developed the model in two types: ideal model and non-ideal model. All of the models utilized equivalent circuits to achieve the characteristics of the PCM. We used SPICE to implement the ideal macro model and the peripheral circuit to verify the model. We also used Verilog-A to develop the non-ideal model, because Verilog-A provides a simple way for formulating math equations. All models we developed have customized parameters. The model helps develop the PCM device.
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