| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 95 === Plasma display is a promising and potential candidate of large size and HDTV market until now because of its reasonable cost, high response time and high color contrast compared with TFT-LCD flat panel display. But it still has space to enhance these merits from the driving waveform design to face the challenge of TFT-LCD for the future large area display. In this thesis, a new driving waveform is proposed to solve some problems of long address period which differ from the conventional one but can broke the bottleneck of contrast and luminance enhancement.
The new driving waveform is trying to reduce address discharge time lag (td) which is composed of the formative time lag (tf) and the statistical time lag (ts), they are related to the electric field strength and the number of priming particles in the cell respectively. We get rid of an allotment of a convention period of ADS driving method, and use multi- reset period and asymmetric settle address voltage to reduce td value to reach the target. The new driving waveform is carried out by a FPGA circuit, DAC circuit with bipolar output voltage and high voltage amplifier circuit. Evaluation of this waveform is accomplished by a 42-inch AC-PDP test panel connecting with driving circuit. We observe discharge emission IR(828,823nm) and color characteristics of the PDP from spectrometer and colorimeter.
We successfully design a 1μs address pulse width and control the td within 0.85μs in the address period. It shows 50% addressing time reduction, 43% luminance enhancement and 34％ contrast improvement compared with conventional waveform. We can further change the dual-scan mode to replace single-scan mode to improve picture quality by using this new waveform.
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