| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 95 === An automation flow of OP Amplifer design is proposed in this thesis. Four common OP Amplifers topologies: telescopic、folded cascade、current mirror and two stage are supported in this flow. It has been implemented by C++ program and HSPICE. Given the required specification and target topology, the tool will offer the circuit with detailed sizes that meets the required specification in the choosed topology. OP Amplifers are the fundamental components in analog circuits that have been used in many kinds of circuits extensively. An automation flow of OP Amplifer design can greatly decrease the design time of the analog circuit.
As CMOS process technology scales, the increasing complexity of VLSI systems also increase the simulation time and verification efforts. In order to reduce the simulation time, the behavioral models of the generated OP circuits are provided simultaneously, which can be used to verify the behavior of the entire system at behavioral level to reduce the system simulation time.
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